Green shading in the line number column means the source is part of the translation unit, red means it is conditionally excluded. Highlighted line numbers link to the translation unit page. Highlighted macros link to the macro page.
1: #ifndef _ASM_X86_MSR_INDEX_H 2: #define _ASM_X86_MSR_INDEX_H 3: 4: /* CPU model specific register (MSR) numbers */ 5: 6: /* x86-64 specific MSRs */ 7: #define MSR_EFER 0xc0000080 /* extended feature register */ 8: #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9: #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10: #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11: #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12: #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13: #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14: #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15: #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16: 17: /* EFER bits: */ 18: #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19: #define _EFER_LME 8 /* Long mode enable */ 20: #define _EFER_LMA 10 /* Long mode active (read-only) */ 21: #define _EFER_NX 11 /* No execute enable */ 22: #define _EFER_SVME 12 /* Enable virtualization */ 23: #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24: #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25: 26: #define EFER_SCE (1<<_EFER_SCE) 27: #define EFER_LME (1<<_EFER_LME) 28: #define EFER_LMA (1<<_EFER_LMA) 29: #define EFER_NX (1<<_EFER_NX) 30: #define EFER_SVME (1<<_EFER_SVME) 31: #define EFER_LMSLE (1<<_EFER_LMSLE) 32: #define EFER_FFXSR (1<<_EFER_FFXSR) 33: 34: /* Intel MSRs. Some also available on other CPUs */ 35: #define MSR_IA32_PERFCTR0 0x000000c1 36: #define MSR_IA32_PERFCTR1 0x000000c2 37: #define MSR_FSB_FREQ 0x000000cd 38: #define MSR_NHM_PLATFORM_INFO 0x000000ce 39: 40: #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 41: #define NHM_C3_AUTO_DEMOTE (1UL << 25) 42: #define NHM_C1_AUTO_DEMOTE (1UL << 26) 43: #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 44: #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 45: #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 46: 47: #define MSR_PLATFORM_INFO 0x000000ce 48: #define MSR_MTRRcap 0x000000fe 49: #define MSR_IA32_BBL_CR_CTL 0x00000119 50: #define MSR_IA32_BBL_CR_CTL3 0x0000011e 51: 52: #define MSR_IA32_SYSENTER_CS 0x00000174 53: #define MSR_IA32_SYSENTER_ESP 0x00000175 54: #define MSR_IA32_SYSENTER_EIP 0x00000176 55: 56: #define MSR_IA32_MCG_CAP 0x00000179 57: #define MSR_IA32_MCG_STATUS 0x0000017a 58: #define MSR_IA32_MCG_CTL 0x0000017b 59: 60: #define MSR_OFFCORE_RSP_0 0x000001a6 61: #define MSR_OFFCORE_RSP_1 0x000001a7 62: #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 63: #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 64: 65: #define MSR_LBR_SELECT 0x000001c8 66: #define MSR_LBR_TOS 0x000001c9 67: #define MSR_LBR_NHM_FROM 0x00000680 68: #define MSR_LBR_NHM_TO 0x000006c0 69: #define MSR_LBR_CORE_FROM 0x00000040 70: #define MSR_LBR_CORE_TO 0x00000060 71: 72: #define MSR_IA32_PEBS_ENABLE 0x000003f1 73: #define MSR_IA32_DS_AREA 0x00000600 74: #define MSR_IA32_PERF_CAPABILITIES 0x00000345 75: #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 76: 77: #define MSR_MTRRfix64K_00000 0x00000250 78: #define MSR_MTRRfix16K_80000 0x00000258 79: #define MSR_MTRRfix16K_A0000 0x00000259 80: #define MSR_MTRRfix4K_C0000 0x00000268 81: #define MSR_MTRRfix4K_C8000 0x00000269 82: #define MSR_MTRRfix4K_D0000 0x0000026a 83: #define MSR_MTRRfix4K_D8000 0x0000026b 84: #define MSR_MTRRfix4K_E0000 0x0000026c 85: #define MSR_MTRRfix4K_E8000 0x0000026d 86: #define MSR_MTRRfix4K_F0000 0x0000026e 87: #define MSR_MTRRfix4K_F8000 0x0000026f 88: #define MSR_MTRRdefType 0x000002ff 89: 90: #define MSR_IA32_CR_PAT 0x00000277 91: 92: #define MSR_IA32_DEBUGCTLMSR 0x000001d9 93: #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 94: #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 95: #define MSR_IA32_LASTINTFROMIP 0x000001dd 96: #define MSR_IA32_LASTINTTOIP 0x000001de 97: 98: /* DEBUGCTLMSR bits (others vary by model): */ 99: #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 100: #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 101: #define DEBUGCTLMSR_TR (1UL << 6) 102: #define DEBUGCTLMSR_BTS (1UL << 7) 103: #define DEBUGCTLMSR_BTINT (1UL << 8) 104: #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 105: #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 106: #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 107: 108: #define MSR_IA32_POWER_CTL 0x000001fc 109: 110: #define MSR_IA32_MC0_CTL 0x00000400 111: #define MSR_IA32_MC0_STATUS 0x00000401 112: #define MSR_IA32_MC0_ADDR 0x00000402 113: #define MSR_IA32_MC0_MISC 0x00000403 114: 115: /* C-state Residency Counters */ 116: #define MSR_PKG_C3_RESIDENCY 0x000003f8 117: #define MSR_PKG_C6_RESIDENCY 0x000003f9 118: #define MSR_PKG_C7_RESIDENCY 0x000003fa 119: #define MSR_CORE_C3_RESIDENCY 0x000003fc 120: #define MSR_CORE_C6_RESIDENCY 0x000003fd 121: #define MSR_CORE_C7_RESIDENCY 0x000003fe 122: #define MSR_PKG_C2_RESIDENCY 0x0000060d 123: #define MSR_PKG_C8_RESIDENCY 0x00000630 124: #define MSR_PKG_C9_RESIDENCY 0x00000631 125: #define MSR_PKG_C10_RESIDENCY 0x00000632 126: 127: /* Run Time Average Power Limiting (RAPL) Interface */ 128: 129: #define MSR_RAPL_POWER_UNIT 0x00000606 130: 131: #define MSR_PKG_POWER_LIMIT 0x00000610 132: #define MSR_PKG_ENERGY_STATUS 0x00000611 133: #define MSR_PKG_PERF_STATUS 0x00000613 134: #define MSR_PKG_POWER_INFO 0x00000614 135: 136: #define MSR_DRAM_POWER_LIMIT 0x00000618 137: #define MSR_DRAM_ENERGY_STATUS 0x00000619 138: #define MSR_DRAM_PERF_STATUS 0x0000061b 139: #define MSR_DRAM_POWER_INFO 0x0000061c 140: 141: #define MSR_PP0_POWER_LIMIT 0x00000638 142: #define MSR_PP0_ENERGY_STATUS 0x00000639 143: #define MSR_PP0_POLICY 0x0000063a 144: #define MSR_PP0_PERF_STATUS 0x0000063b 145: 146: #define MSR_PP1_POWER_LIMIT 0x00000640 147: #define MSR_PP1_ENERGY_STATUS 0x00000641 148: #define MSR_PP1_POLICY 0x00000642 149: 150: #define MSR_CORE_C1_RES 0x00000660 151: 152: #define MSR_AMD64_MC0_MASK 0xc0010044 153: 154: #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 155: #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 156: #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 157: #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 158: 159: #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 160: 161: /* These are consecutive and not in the normal 4er MCE bank block */ 162: #define MSR_IA32_MC0_CTL2 0x00000280 163: #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 164: 165: #define MSR_P6_PERFCTR0 0x000000c1 166: #define MSR_P6_PERFCTR1 0x000000c2 167: #define MSR_P6_EVNTSEL0 0x00000186 168: #define MSR_P6_EVNTSEL1 0x00000187 169: 170: #define MSR_KNC_PERFCTR0 0x00000020 171: #define MSR_KNC_PERFCTR1 0x00000021 172: #define MSR_KNC_EVNTSEL0 0x00000028 173: #define MSR_KNC_EVNTSEL1 0x00000029 174: 175: /* Alternative perfctr range with full access. */ 176: #define MSR_IA32_PMC0 0x000004c1 177: 178: /* AMD64 MSRs. Not complete. See the architecture manual for a more 179: complete list. */ 180: 181: #define MSR_AMD64_PATCH_LEVEL 0x0000008b 182: #define MSR_AMD64_TSC_RATIO 0xc0000104 183: #define MSR_AMD64_NB_CFG 0xc001001f 184: #define MSR_AMD64_PATCH_LOADER 0xc0010020 185: #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 186: #define MSR_AMD64_OSVW_STATUS 0xc0010141 187: #define MSR_AMD64_DC_CFG 0xc0011022 188: #define MSR_AMD64_BU_CFG2 0xc001102a 189: #define MSR_AMD64_IBSFETCHCTL 0xc0011030 190: #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 191: #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 192: #define MSR_AMD64_IBSFETCH_REG_COUNT 3 193: #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 194: #define MSR_AMD64_IBSOPCTL 0xc0011033 195: #define MSR_AMD64_IBSOPRIP 0xc0011034 196: #define MSR_AMD64_IBSOPDATA 0xc0011035 197: #define MSR_AMD64_IBSOPDATA2 0xc0011036 198: #define MSR_AMD64_IBSOPDATA3 0xc0011037 199: #define MSR_AMD64_IBSDCLINAD 0xc0011038 200: #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 201: #define MSR_AMD64_IBSOP_REG_COUNT 7 202: #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 203: #define MSR_AMD64_IBSCTL 0xc001103a 204: #define MSR_AMD64_IBSBRTARGET 0xc001103b 205: #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 206: 207: /* Fam 16h MSRs */ 208: #define MSR_F16H_L2I_PERF_CTL 0xc0010230 209: #define MSR_F16H_L2I_PERF_CTR 0xc0010231 210: 211: /* Fam 15h MSRs */ 212: #define MSR_F15H_PERF_CTL 0xc0010200 213: #define MSR_F15H_PERF_CTR 0xc0010201 214: #define MSR_F15H_NB_PERF_CTL 0xc0010240 215: #define MSR_F15H_NB_PERF_CTR 0xc0010241 216: 217: /* Fam 10h MSRs */ 218: #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 219: #define FAM10H_MMIO_CONF_ENABLE (1<<0) 220: #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 221: #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 222: #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 223: #define FAM10H_MMIO_CONF_BASE_SHIFT 20 224: #define MSR_FAM10H_NODE_ID 0xc001100c 225: 226: /* K8 MSRs */ 227: #define MSR_K8_TOP_MEM1 0xc001001a 228: #define MSR_K8_TOP_MEM2 0xc001001d 229: #define MSR_K8_SYSCFG 0xc0010010 230: #define MSR_K8_INT_PENDING_MSG 0xc0010055 231: /* C1E active bits in int pending message */ 232: #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 233: #define MSR_K8_TSEG_ADDR 0xc0010112 234: #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 235: #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 236: #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 237: 238: /* K7 MSRs */ 239: #define MSR_K7_EVNTSEL0 0xc0010000 240: #define MSR_K7_PERFCTR0 0xc0010004 241: #define MSR_K7_EVNTSEL1 0xc0010001 242: #define MSR_K7_PERFCTR1 0xc0010005 243: #define MSR_K7_EVNTSEL2 0xc0010002 244: #define MSR_K7_PERFCTR2 0xc0010006 245: #define MSR_K7_EVNTSEL3 0xc0010003 246: #define MSR_K7_PERFCTR3 0xc0010007 247: #define MSR_K7_CLK_CTL 0xc001001b 248: #define MSR_K7_HWCR 0xc0010015 249: #define MSR_K7_FID_VID_CTL 0xc0010041 250: #define MSR_K7_FID_VID_STATUS 0xc0010042 251: 252: /* K6 MSRs */ 253: #define MSR_K6_WHCR 0xc0000082 254: #define MSR_K6_UWCCR 0xc0000085 255: #define MSR_K6_EPMR 0xc0000086 256: #define MSR_K6_PSOR 0xc0000087 257: #define MSR_K6_PFIR 0xc0000088 258: 259: /* Centaur-Hauls/IDT defined MSRs. */ 260: #define MSR_IDT_FCR1 0x00000107 261: #define MSR_IDT_FCR2 0x00000108 262: #define MSR_IDT_FCR3 0x00000109 263: #define MSR_IDT_FCR4 0x0000010a 264: 265: #define MSR_IDT_MCR0 0x00000110 266: #define MSR_IDT_MCR1 0x00000111 267: #define MSR_IDT_MCR2 0x00000112 268: #define MSR_IDT_MCR3 0x00000113 269: #define MSR_IDT_MCR4 0x00000114 270: #define MSR_IDT_MCR5 0x00000115 271: #define MSR_IDT_MCR6 0x00000116 272: #define MSR_IDT_MCR7 0x00000117 273: #define MSR_IDT_MCR_CTRL 0x00000120 274: 275: /* VIA Cyrix defined MSRs*/ 276: #define MSR_VIA_FCR 0x00001107 277: #define MSR_VIA_LONGHAUL 0x0000110a 278: #define MSR_VIA_RNG 0x0000110b 279: #define MSR_VIA_BCR2 0x00001147 280: 281: /* Transmeta defined MSRs */ 282: #define MSR_TMTA_LONGRUN_CTRL 0x80868010 283: #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 284: #define MSR_TMTA_LRTI_READOUT 0x80868018 285: #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 286: 287: /* Intel defined MSRs. */ 288: #define MSR_IA32_P5_MC_ADDR 0x00000000 289: #define MSR_IA32_P5_MC_TYPE 0x00000001 290: #define MSR_IA32_TSC 0x00000010 291: #define MSR_IA32_PLATFORM_ID 0x00000017 292: #define MSR_IA32_EBL_CR_POWERON 0x0000002a 293: #define MSR_EBC_FREQUENCY_ID 0x0000002c 294: #define MSR_SMI_COUNT 0x00000034 295: #define MSR_IA32_FEATURE_CONTROL 0x0000003a 296: #define MSR_IA32_TSC_ADJUST 0x0000003b 297: 298: #define FEATURE_CONTROL_LOCKED (1<<0) 299: #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 300: #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 301: 302: #define MSR_IA32_APICBASE 0x0000001b 303: #define MSR_IA32_APICBASE_BSP (1<<8) 304: #define MSR_IA32_APICBASE_ENABLE (1<<11) 305: #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 306: 307: #define MSR_IA32_TSCDEADLINE 0x000006e0 308: 309: #define MSR_IA32_UCODE_WRITE 0x00000079 310: #define MSR_IA32_UCODE_REV 0x0000008b 311: 312: #define MSR_IA32_PERF_STATUS 0x00000198 313: #define MSR_IA32_PERF_CTL 0x00000199 314: #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 315: #define MSR_AMD_PERF_STATUS 0xc0010063 316: #define MSR_AMD_PERF_CTL 0xc0010062 317: 318: #define MSR_IA32_MPERF 0x000000e7 319: #define MSR_IA32_APERF 0x000000e8 320: 321: #define MSR_IA32_THERM_CONTROL 0x0000019a 322: #define MSR_IA32_THERM_INTERRUPT 0x0000019b 323: 324: #define THERM_INT_HIGH_ENABLE (1 << 0) 325: #define THERM_INT_LOW_ENABLE (1 << 1) 326: #define THERM_INT_PLN_ENABLE (1 << 24) 327: 328: #define MSR_IA32_THERM_STATUS 0x0000019c 329: 330: #define THERM_STATUS_PROCHOT (1 << 0) 331: #define THERM_STATUS_POWER_LIMIT (1 << 10) 332: 333: #define MSR_THERM2_CTL 0x0000019d 334: 335: #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 336: 337: #define MSR_IA32_MISC_ENABLE 0x000001a0 338: 339: #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 340: 341: #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 342: #define ENERGY_PERF_BIAS_PERFORMANCE 0 343: #define ENERGY_PERF_BIAS_NORMAL 6 344: #define ENERGY_PERF_BIAS_POWERSAVE 15 345: 346: #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 347: 348: #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 349: #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 350: 351: #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 352: 353: #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 354: #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 355: #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 356: 357: /* Thermal Thresholds Support */ 358: #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 359: #define THERM_SHIFT_THRESHOLD0 8 360: #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 361: #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 362: #define THERM_SHIFT_THRESHOLD1 16 363: #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 364: #define THERM_STATUS_THRESHOLD0 (1 << 6) 365: #define THERM_LOG_THRESHOLD0 (1 << 7) 366: #define THERM_STATUS_THRESHOLD1 (1 << 8) 367: #define THERM_LOG_THRESHOLD1 (1 << 9) 368: 369: /* MISC_ENABLE bits: architectural */ 370: #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 371: #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 372: #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 373: #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 374: #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 375: #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 376: #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 377: #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 378: #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 379: #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 380: 381: /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 382: #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 383: #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 384: #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 385: #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 386: #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 387: #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 388: #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 389: #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 390: #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 391: #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 392: #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 393: #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 394: #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 395: #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 396: #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 397: 398: #define MSR_IA32_TSC_DEADLINE 0x000006E0 399: 400: /* P4/Xeon+ specific */ 401: #define MSR_IA32_MCG_EAX 0x00000180 402: #define MSR_IA32_MCG_EBX 0x00000181 403: #define MSR_IA32_MCG_ECX 0x00000182 404: #define MSR_IA32_MCG_EDX 0x00000183 405: #define MSR_IA32_MCG_ESI 0x00000184 406: #define MSR_IA32_MCG_EDI 0x00000185 407: #define MSR_IA32_MCG_EBP 0x00000186 408: #define MSR_IA32_MCG_ESP 0x00000187 409: #define MSR_IA32_MCG_EFLAGS 0x00000188 410: #define MSR_IA32_MCG_EIP 0x00000189 411: #define MSR_IA32_MCG_RESERVED 0x0000018a 412: 413: /* Pentium IV performance counter MSRs */ 414: #define MSR_P4_BPU_PERFCTR0 0x00000300 415: #define MSR_P4_BPU_PERFCTR1 0x00000301 416: #define MSR_P4_BPU_PERFCTR2 0x00000302 417: #define MSR_P4_BPU_PERFCTR3 0x00000303 418: #define MSR_P4_MS_PERFCTR0 0x00000304 419: #define MSR_P4_MS_PERFCTR1 0x00000305 420: #define MSR_P4_MS_PERFCTR2 0x00000306 421: #define MSR_P4_MS_PERFCTR3 0x00000307 422: #define MSR_P4_FLAME_PERFCTR0 0x00000308 423: #define MSR_P4_FLAME_PERFCTR1 0x00000309 424: #define MSR_P4_FLAME_PERFCTR2 0x0000030a 425: #define MSR_P4_FLAME_PERFCTR3 0x0000030b 426: #define MSR_P4_IQ_PERFCTR0 0x0000030c 427: #define MSR_P4_IQ_PERFCTR1 0x0000030d 428: #define MSR_P4_IQ_PERFCTR2 0x0000030e 429: #define MSR_P4_IQ_PERFCTR3 0x0000030f 430: #define MSR_P4_IQ_PERFCTR4 0x00000310 431: #define MSR_P4_IQ_PERFCTR5 0x00000311 432: #define MSR_P4_BPU_CCCR0 0x00000360 433: #define MSR_P4_BPU_CCCR1 0x00000361 434: #define MSR_P4_BPU_CCCR2 0x00000362 435: #define MSR_P4_BPU_CCCR3 0x00000363 436: #define MSR_P4_MS_CCCR0 0x00000364 437: #define MSR_P4_MS_CCCR1 0x00000365 438: #define MSR_P4_MS_CCCR2 0x00000366 439: #define MSR_P4_MS_CCCR3 0x00000367 440: #define MSR_P4_FLAME_CCCR0 0x00000368 441: #define MSR_P4_FLAME_CCCR1 0x00000369 442: #define MSR_P4_FLAME_CCCR2 0x0000036a 443: #define MSR_P4_FLAME_CCCR3 0x0000036b 444: #define MSR_P4_IQ_CCCR0 0x0000036c 445: #define MSR_P4_IQ_CCCR1 0x0000036d 446: #define MSR_P4_IQ_CCCR2 0x0000036e 447: #define MSR_P4_IQ_CCCR3 0x0000036f 448: #define MSR_P4_IQ_CCCR4 0x00000370 449: #define MSR_P4_IQ_CCCR5 0x00000371 450: #define MSR_P4_ALF_ESCR0 0x000003ca 451: #define MSR_P4_ALF_ESCR1 0x000003cb 452: #define MSR_P4_BPU_ESCR0 0x000003b2 453: #define MSR_P4_BPU_ESCR1 0x000003b3 454: #define MSR_P4_BSU_ESCR0 0x000003a0 455: #define MSR_P4_BSU_ESCR1 0x000003a1 456: #define MSR_P4_CRU_ESCR0 0x000003b8 457: #define MSR_P4_CRU_ESCR1 0x000003b9 458: #define MSR_P4_CRU_ESCR2 0x000003cc 459: #define MSR_P4_CRU_ESCR3 0x000003cd 460: #define MSR_P4_CRU_ESCR4 0x000003e0 461: #define MSR_P4_CRU_ESCR5 0x000003e1 462: #define MSR_P4_DAC_ESCR0 0x000003a8 463: #define MSR_P4_DAC_ESCR1 0x000003a9 464: #define MSR_P4_FIRM_ESCR0 0x000003a4 465: #define MSR_P4_FIRM_ESCR1 0x000003a5 466: #define MSR_P4_FLAME_ESCR0 0x000003a6 467: #define MSR_P4_FLAME_ESCR1 0x000003a7 468: #define MSR_P4_FSB_ESCR0 0x000003a2 469: #define MSR_P4_FSB_ESCR1 0x000003a3 470: #define MSR_P4_IQ_ESCR0 0x000003ba 471: #define MSR_P4_IQ_ESCR1 0x000003bb 472: #define MSR_P4_IS_ESCR0 0x000003b4 473: #define MSR_P4_IS_ESCR1 0x000003b5 474: #define MSR_P4_ITLB_ESCR0 0x000003b6 475: #define MSR_P4_ITLB_ESCR1 0x000003b7 476: #define MSR_P4_IX_ESCR0 0x000003c8 477: #define MSR_P4_IX_ESCR1 0x000003c9 478: #define MSR_P4_MOB_ESCR0 0x000003aa 479: #define MSR_P4_MOB_ESCR1 0x000003ab 480: #define MSR_P4_MS_ESCR0 0x000003c0 481: #define MSR_P4_MS_ESCR1 0x000003c1 482: #define MSR_P4_PMH_ESCR0 0x000003ac 483: #define MSR_P4_PMH_ESCR1 0x000003ad 484: #define MSR_P4_RAT_ESCR0 0x000003bc 485: #define MSR_P4_RAT_ESCR1 0x000003bd 486: #define MSR_P4_SAAT_ESCR0 0x000003ae 487: #define MSR_P4_SAAT_ESCR1 0x000003af 488: #define MSR_P4_SSU_ESCR0 0x000003be 489: #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 490: 491: #define MSR_P4_TBPU_ESCR0 0x000003c2 492: #define MSR_P4_TBPU_ESCR1 0x000003c3 493: #define MSR_P4_TC_ESCR0 0x000003c4 494: #define MSR_P4_TC_ESCR1 0x000003c5 495: #define MSR_P4_U2L_ESCR0 0x000003b0 496: #define MSR_P4_U2L_ESCR1 0x000003b1 497: 498: #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 499: 500: /* Intel Core-based CPU performance counters */ 501: #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 502: #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 503: #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 504: #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 505: #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 506: #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 507: #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 508: 509: /* Geode defined MSRs */ 510: #define MSR_GEODE_BUSCONT_CONF0 0x00001900 511: 512: /* Intel VT MSRs */ 513: #define MSR_IA32_VMX_BASIC 0x00000480 514: #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 515: #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 516: #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 517: #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 518: #define MSR_IA32_VMX_MISC 0x00000485 519: #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 520: #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 521: #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 522: #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 523: #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 524: #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 525: #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 526: #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 527: #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 528: #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 529: #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 530: 531: /* VMX_BASIC bits and bitmasks */ 532: #define VMX_BASIC_VMCS_SIZE_SHIFT 32 533: #define VMX_BASIC_64 0x0001000000000000LLU 534: #define VMX_BASIC_MEM_TYPE_SHIFT 50 535: #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 536: #define VMX_BASIC_MEM_TYPE_WB 6LLU 537: #define VMX_BASIC_INOUT 0x0040000000000000LLU 538: 539: /* MSR_IA32_VMX_MISC bits */ 540: #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 541: #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 542: /* AMD-V MSRs */ 543: 544: #define MSR_VM_CR 0xc0010114 545: #define MSR_VM_IGNNE 0xc0010115 546: #define MSR_VM_HSAVE_PA 0xc0010117 547: 548: #endif /* _ASM_X86_MSR_INDEX_H */ 549: